Testing Interconnects in a System Chip
نویسندگان
چکیده
Testing of interconnects on a printed circuit board has been studied and the procedure has been standardized in the IEEE 1149.1 (JTAG) standard. The Sysem-on-Chip (SOC) technology allows us to integrate on the same chip, most of the electronics on a PCB. However, since an SOC operates at a much higher speed and has a very large packaging density, testing its interconnects is different. For example, one must address the crosstalk faults with chip-level interconnects. Not much literature exists on the topic of testing interconnects in core-based systems. We propose a graph-theoretic framework for the problem and a genetic algorithm for testing core interconnects. Our algorithm addresses the issues of test application time, test area overhead, fault-coverage, and test power.
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